The present invention relates generally to digital testers, and in particular to automatic test equipment (ATE) used for testing very large system integration (VLSI) digital devices.
VLSI devices such as microprocessors and memory devices are commonly used in computers and electronic products. To ensure that these devices perform properly, a test is applied to them at various points during manufacturing process to measure their performance.
To test a VLSI device, ATE (or tester) is commonly used. Traditional ATE performs the test using a typical test method commonly referred xe2x80x9cgo/no-goxe2x80x9d method. Traditional ATE has several main units for performing the test. A compare unit compares output data of the device under test (DUT) with expected data provided by a pattern data memory. After the compare unit compares the output data, a data timing strobe unit such as a D-Q latch strobes the output data at a fixed time to obtain a single pass/fail result for each location of the pattern memory. A capture unit receives the pass/fail result to indicate if the device has either passed or failed the test. Thus, in traditional ATE, the information available after a pattern test executes is either xe2x80x9call pattern locations passxe2x80x9d or xe2x80x9cat least one pattern location failsxe2x80x9d. As VLSI devices progressively operate with higher speed, new techniques are needed to ensure that a device""s output signals propagate to other devices with correct timing relationships for the application environment. For example, one common technique is to allow the device sending a data signal to also send a timing reference signal (known as a clock or strobe) used to locate the point in time that a data signal (or group of such data signals) has the correct one or zero data state. Testing output pin performance of these so-called source referenced devices is extremely difficult with traditional ATE. Traditional ATE use an internally generated timing reference and use a pre-determined delta from that time to look for valid data on a device output pin. The problem is that the valid data timing reference needs to come from the device strobe, it varies from one test pattern location to the next, and it cannot be accurately pre-determined.
To use traditional ATE on source referenced devices, the test patterns are iterated many times while the time values are incremented to find pass/fail boundaries. The timing of the pass/fail boundary is compared between the output data signal and the output strobe signal to determine if the required timing relationship is correct. This iterative pattern execution is very time consuming. In addition, it does not accurately determine the timing relationship for each strobe/data instance. Instead, it lumps all of the results together and can either pass marginally bad results or fail marginally good results. Variability of device timings can result in a good device in the application environment failing a test in the ATE environment.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for improved ATE.